With the scaling of integrated circuits, metal-oxide-semiconductor (MOS) devices become increasingly smaller. The junction depths of the MOS devices are reduced accordingly. This reduction causes technical difficulties during the formation processes. For example, small MOS devices demand high dopant concentrations in source and drain regions to reduce resistivity in the source and drain regions. Controlling implantation depth to form shallow junctions in source and drain extension regions of small-scale devices is also difficult. In addition, since the distance between source/drain silicide regions and the respective source/drain junctions is small, the leakage currents are high and drive currents are low.
To solve the above-discussed problems, raised source and drain regions have been formed. FIG. 1 illustrates a commonly formed MOS device having raised source/drain regions. In its formation, a gate stack includes gate dielectric 4 and gate electrode 6, and is formed on substrate 2. Lightly doped source/drain (LDD) regions 8 are formed by implantation. Gate spacers 10 are then formed. Then an epitaxial growth is performed to grow crystalline silicon layers 12 on substrate 2. Source and drain regions 14 are formed by an implantation, followed by the formation of source/drain silicide regions 16.
The conventional MOS devices as shown in FIG. 1 suffer drawbacks. Since PMOS and NMOS devices have different band-gaps, to reduce possible Schottky barrier heights between silicide regions 16 and the underlying semiconductor material, dual metal schemes are needed, in which the silicide regions of PMOS and NMOS devices comprise different metals. Accordingly, the silicide regions of PMOS and NMOS devices are formed separately, incurring high production cost.
Accordingly, what is needed in the art is a semiconductor device that incorporates raised source/drain regions thereof, to benefit from associated reduced leakage currents and increased drive currents while at the same time overcoming the deficiencies of the prior art.